The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique which may be effectively applied to an ultraspeed LSI having a memory section and a logic section.
General gate array techniques are disclosed, for example, in G.B. Patent Number 2,104,284, Takahashi et al., U.S. patent application Ser. No. 946,608, Kawashima, filed on Dec. 29, 1986, now U.S. Pat. No. 4,766,475, and also in the articles by Takahashi and Nishimura et al. in the July 1986 issue of "Denshi Zairyo (Electronic Materials)", a journal, pp. 104-109 and pp. 110-115, respectively.
To respond to the demand for achievement of high-speed computers, memory LSI's having peripheral logic functions additionally imparted thereto (hereinafter referred to as "logical memory LSI's" or "memoried logic LSIs") have recently been used as memory LSI's for large-sized computers by way of example.
These memory LSIs are introduced in the articles contributed to the same issue of the above-described journal by Shimizu and Fujii et al., pp. 66-71 and pp. 86-91, respectively.
The above-described article written by Fujii et al. also discloses a gate array IC wherein an I/O (input/output) section and a logic section are connected together by a third-level Al interconnection which is extended above a memory section.